Research Abstracts - 2006

Enabling Automatic Analog/RF Circuit Sizing

Varun Aggarwal & Una-May O'Reilly

WHAT AND HOW?

For every new silicon technology, an existing analog/RF circuit has to be resized to meet the design specifications. This process is by no means trivial and requires experienced analog design engineering and a lengthy fully customized design flow. Design of RF circuits is an even greater challenge. The process of schematic and layout design which is (somewhat) decoupled for analog circuits is completely coupled for RF circuits. The general practice in the industry is to choose a topology from a repertoire of topologies. The topology choice is guided by the intuition of the engineer, as to which one of them will be optimal for the system-level performance specification. The chosen topology is then sized to meet the specifications.

We are interested in developing algorithms for automatic sizing of circuit topologies according to designer-formulated specifications. This problem has been addressed by stochastic optimization (products of Analog Design Automation, NeoLinear Inc. [1]), structural optimization approaches (Geometric Programming [2]) and a plethora of knowledge-based approaches. The knowledge based approaches seek to size the circuit using a rule-set derived from expert knowledge. On the other hand, optimization considers the size of components as input variables and optimizes on the value of specification parameters (which are a function of the input variables). The optimized function here implies the the mapping between performance of the circuit and the sizes of devices, which can be determined for individual points by SPICE runs.

The knowledge based approaches in isolation are of limited power, but are useful for expressing constraints of the optimization problem. From the point of view of optimization, knowledge about the function to be optimized is scant and unnecessary.The function can be treated as a black box. Yet, the large running time of SPICE simulations makes function evaluation computationally very expensive. We want to answer: What is the most efficient way to optimize when the objective function is a black-box and its evaluation is computationally very expensive? The possible algorithmic approaches could include stochastic algorithms or the ones that model the function with a structural form apt for convex optimization. We have taken an unbiased view of these algorithms and want to study their effectiveness in solving representative problems. We believe that an efficient algorithm will be a hybrid of the two approaches. We are working towards developing such an algorithm to get speedy sizing of analog circuit with minimum calls to SPICE for performance evaluation.

We want to extend this strategy to RF circuits, which require consideration of layout parasitics in the optimization loop. To facilitate the same, we plan to use reduced order models for inductors/interconnects to incorporate layout affects. These models are fairly accurate and fast to simulate. Our algorithm design (for both analog/RF design) would consider the block-specific performance parameters, power and area, with the objective of robustness (from corners, drifts) being pervasive.

The second part of our research is more radical in nature. In the above description, we formulated the problem of sizing a given topology for a set of specifications. We want to explore the option of providing the feasible space information for each topology for a given block (for instance, amplifier) a priori to the designer. A database of optimal design solutions which the topology can achieve will be stored in a database. For instance, Topology A may achieve gain of 5000, a phase margin of 55 degrees at lower power than topology B, but Topology B may achieve a gain of 10,000 and a phase margin of 30 degrees at lower power than Topology A. Given this information, the designer can choose the topology for system-level specifications. In fact, the designer may want to change the specification of the block (and compensate with some other block in system) to facilitate more optimal system-level performance. Thus, the Performance Space Model (PSM) (or Feasibility Space Model) not only allows the designer to decide 'which topology', but also decide the performance specifications for the blocks. This will enable a true System Level Design approach to analog/RF circuit synthesis [3].

This approach to design motivates algorithms that address two problems. The first problem is generation of PSMs for circuits. The problem of PSM can be addressed one way by casting it as an optimization problem. However, it is important to note that the primary requirement of the solution is different from the same of the algorithms discussed in the first part. The primary objective of the algorithm is the correct model of performance space rather than high speed. Speed can be compromised upon, since for a given topology and technology, the PSM is generated once and stored. The second interesting problem is to decide the performance specification for each block given the specifications and structure of the whole system and PSMs for all topologies. This forms a discrete optimization problem, whose solution can enable Optimal Automatic System Level Design.

HOW?

For the first problem, we are working on two fronts. The first front comprises of a one-to-one comparison and analysis of structured and stochastic approaches of circuit optimization. For this, we have coded evolutionary algorithms (specifically Particle Swarm Optimization [4]) for optimization of analog circuits. In the next step, we plan to use convex optimization for optimization. The analysis and comparison of these approaches will lead us to the primary question of the appropriate scheme to optimize an unstructured function with expensive evaluation. The analysis on the second front addresses this, where we are preparing a theoretical model to optimize black-box functions in least number of function evaluations (SPICE runs). This model brings together more than one optimization scheme in a resource allocation framework with efficient model building of the function space.

For PSMs, we have divided the domain into two parts, i. When PSM can be re-cast as a multi-objective optimization (MOO) problem and ii. When PSM implies modeling of the feasible space of the output of a function given the constraints on the input and the function definition. For addressing MOO, we have coded a constraint-based multi-objective particle swarm optimization. We are extending it to include parallel and cooperative models of optimization for accurate convergence to the correct performance front. For modeling of feasible space, we are at a concept and proposal stage. The ideas of a system level optimizer could be put in practice by adapting Bayesian Optimization for the given problem.

References:

[1] R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, and J. R. Hellums. ANACONDA: Robust synthesis of analog circuits via stochastic pattern search. in Proc. IEEE Custom Integrated Circuits Conf. , pp. 567?570, 1999.

[2] S. Boyd and S. J. Kim. Geometric Programming for Circuit Optimization. In Prooceedings of International Symposium on Physical Design (ISPD) , pp. 44-46, April 2005.

[3] G. G. E. Gielen, Trent McConaghy, Tom Eeckelaert. Performance space modeling for hierarchical synthesis of analog integrated circuits. In Design Automation Conference, 881-886, 2005.

[4] J. Kennedy and R. Eberhart. Particle swarm optimization. In IEEE International Conference on Neural Networks , Vol. 4, pp. 1942?1948, 1995.