| Publication Title: |
Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage |
| Publication Author: |
Heo, Seongmoo |
| Additional Authors: |
Krste Asanovic |
| LCS Document Number: |
MIT-LCS-TR-957 |
| Publication Date: |
7-12-2004 |
| LCS Group: |
Computer Architecture |
| Additional URL: |
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| Abstract: |
| Digital circuits often have a critical path that runs through a small
subset of the component subblocks, but where the path changes dynamically
during operation. Dynamically resizable static CMOS (DRCMOS) logic is
proposed as a fine-grain leakage reduction technique that dynamically
downsizes transistors in inactive subblocks while maintaining speed in
subblocks along the current critical path. A 64-entry register free list
and a 64-entry pick-two arbiter are used to evaluate DRCMOS. DRCMOS is
shown to give a 50% reduction in total power for equal delay in a
70 nm technology.
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