| Publication Title: |
A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-level Computation |
| Publication Author: |
Wentzlaff, David |
| Additional Authors: |
Anant Agarwal |
| LCS Document Number: |
MIT-LCS-TR-944 |
| Publication Date: |
4-13-2004 |
| LCS Group: |
Computer Architecture |
| Additional URL: |
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| Abstract: |
| General purpose computing architectures are being called on to work on a
more diverse application mix every day. This has been fueled by the need
for reduced time to market and economies of scale that are the hallmarks
of software on general purpose microprocessors. As this application mix
expands, application domains such as bit-level computation, which has
primarily been the domain of ASICs and FPGAs, will need to be effectively
handled by general purpose hardware. Examples of bit-level applications
include Ethernet framing, forward error correction encoding/decoding, and
efficient state machine implementation.
In this paper we compare how differing computational structures such as
ASICs, FPGAs, tiled architectures, and superscalar microprocessors are
able to compete on bit-level communication applications. A quantitative
comparison in terms of absolute performance and performance per area will
be presented. These results show that although modest gains~(2-3x) in
absolute performance can be achieved when using FPGAs versus tuned
microprocessor implementations, it is the significantly larger gains~(2-3
orders of magnitude) that can be achieved in performance per area that
will motivate work on supporting bit-level computation in a general
purpose fashion in the future. |
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