LCS Publication Details
Publication Title: StarT-Voyager: Hardware Engineering Specifications (Version 4.0)
Publication Author: Ang, Boon S.
Additional Authors: Derek Chiou
LCS Document Number: MIT-LCS-TM-385
Publication Date: 3-11-1999
LCS Group: No Group Specified
Additional URL:
StarT Voyager is a parallel system designed to support both message passing and coherent dis tributed shared memory. StarT Voyager is constructed from a collection of commercial SMPs connected by a fast network which interfaces to each SMP's coherent memory bus via a Network Endpoint Subsystem (NES) card. Each SMP, referred to as a site, is a desktop class, commercial, dual PowerPC 604 SMP It uses a stock PC/workstation class motherboard which can accommodate two processor cards. Each processor card normally contains one 604 processor and an in-line L 2 cache. For StarT Voyager, we replace one of the two processor cards in each SMP site with an NES card, making each site into a uniprocessor system. This 604 processor, referred to as the application processor or aP, runs a copy of AIX augmented with a parallel layer to coordinate parallel job execution.
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