LCS Publication Details
Publication Title: VIRTUAL WIRES: OVERCOMING PIN LIMITATIONS IN FPGA-BASED LOGIC EMULATORS
Publication Author: Babb, Jonathan
Additional Authors: Tessier, Russell and Agarwal, Anant
LCS Document Number: MIT-LCS-TM-491
Publication Date: 11-1-1992
LCS Group: No Group Specified
Additional URL: No URL Given
Abstract:
Existing FPGA-based logic emulators suffer from limited inter-chip communication bandwidth, resulting in low gate utilization (10 20 percent). This resource imbalance increases the number of chips needed to emulate a particular logic design and thereby decreases emulation speed, since signals must cross more chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire). These logical wires are not active simultaneously are only switched at emulation clock speeds.
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