Introduction

Pipelining reduces the number of logic levels between registers and is usually employed by digital systems designers to increase achievable clock frequency (Figure 1). But the time slack obtained from pipelining can also be used to reduce power consumption by lowering supply voltage at a fixed clock frequency (Figure 2). This technique can be very effective for digital systems with fixed throughput requirements and highly parallel computations. Supply voltage scaling is by far one of the most effective techniques for trading time slack for power. Supply voltage reduction leads to a quadratic reduction in active power and also a super-linear reduction in leakage power, as leakage current has a strong dependency on drain voltage in deep submicron processes. A parallel architecture could also be used to provide excess performance to trade for lower power, but pipelining has the advantage of a lower area penalty. Power reductions from pipelining are eventually limited by the power overhead of the additional pipeline latches or flip-flops required for each additional pipe stage, leading to a power-optimal level of pipelining.

Figure 1. Traditional Pipelining.

Figure 2. Trading Time Slack for Power.

Figure 3 shows how pipelining can be expoited as a low-power tool while keeping the same delay using a power-delay curve (PD curve). Figure 4 shows that there is a power-optimal pipelining point which leads to the lowest power consumption for a given throuput.

Figure 3. Pipelining as a Low-Power Tool.

Figure 4. Power-Optimal Pipelining.

We study how power-optimal pipelining varies for different operating regimes in deep submicron technology. We examine the tradeoffs between pipeline depth, supply voltage, threshold voltage, and total power using circuit-level simulations and analytical models. We also explore the effect of activity factor and clock gating.

Approach

We examine power-optimal pipelining in deep submicron technology, both analytically and by simulation. Simulation uses a 70 nm predictive process with a fanout-of-four inverter chain model including input/output flip-flops.

Progress

Figure 5 and 6 show the analytical trends of switching power and leakage power resepectively.

Figure 5. Analytical Trend: Pipelining and Switching Power.

Figure 6. Analytical Trend: Pipelining and Leakage Power

The simulation results show that power-optimal logic depth is 6 to 8 FO4 and optimal power saving varies from 55 to 80 % compared to a 24 FO4 logic depth, depending on threshold voltage, activity factor, and presence of clock-gating (FO4 is a unit delay of a gate driving four gates of the same kind).

We found the following insights into power-optimal pipelining. First, power-optimal logic depth decreases and optimal power savings increase for larger activity factors, where switching power dominates over leakage and idle power. Second, pipelining is more effective with lower threshold voltages at high activity factors, but higher threshold voltages give better results at lower activity factors where leakage current dominates. Lastly, clock-gating enables deeper pipelining and more power saving because it reduces timing element overhead when the activity factor is low.

Research Support

This work was partly funded by the NSF CAREER Award CCR-0093354, NSF ITR award CCR-0219545, and a donation from Intel Corporation.

References

[1] Seongmoo Heo and Krste Asanovic. Power-Optimal Pipelining in Deep Submicron Technology. In International Symposium on Low Power Electronics and Design (ISLPED) , pp. 218-223, Newport Beach, CA, USA, August 2004.