Introduction

As advances are made in low-power processors, the portion of the system's energy budget that must be allocated to DRAM becomes more and more significant. In order to reduce this energy requirement, we have been developing and evaluating DRAM subsystems that maintain acceptable performance while dramatically reducing the energy consumed. We have designed and implemented a hierarchical DRAM subsystem and developed a cycle-accurate simulator to evaluate the system's performance and energy requirements. We are currently evaluating the energy-performance tradeoffs of a number of controller policies.

The system is physically implemented on an FPGA with attached DDR-II SDRAM chips. The FPGA and DRAM chips will be used to measure the actual energy consumption of DRAM operations. These measurements may then be used to calibrate the simulator. The simulator interfaces with the SCALE group's SCALE simulator, providing useful benchmarking for the memory system's performance.

Method

The DRAM subsystem is a pipelined, hierarchical structure consisting of a number of independent memory channels. A single processor interface is responsible for accepting memory requests, dispatching them to the appropriate channels, and returning completed results to the processor. Each channel contains an independent request queue and scheduler, which dispatches memory requests to a DRAM controller. The request dispatch policy, access scheduling policy, and DRAM power state management policies are implemented by independent modules. These modules may be easily replaced to implement and evaluate different policies. Each of these policies is to be characterized in terms of performance impact and energy consumption for a series of benchmarks.

Progress

The DRAM subsystem has been written, synthesized, and verified in verilog. We have also written the system simulator and integrated it with the SCALE simulator. The FPGA/DRAM board has been assembled, and we are currently testing the functional correctness of the DRAM subsystem in live hardware.

Future

Once the functional verification of the DRAM system is complete, we will be able to gather accurate energy measurements for use in the simulator. Once we have determined the optimal policies, we will be able to implement these in the memory system for the first SCALE test processor.

Other work that remains to be done involves the conception and characterization of new policies. Also, our work has focused primarily on hardware. The development of complementary software policies could greatly enhance the effectiveness of the system.

Research Support

This work was partly funded by the DARPA HPCS/SGI Ultraviolet project, NSF CAREER Award CCR-0093354, the Cambridge-MIT Institute, and equipment donations from Xilinx and Intel.