Research Abstracts - 2007

Multiprocessor Chip for Modular Software

Jack B. Dennis

Introduction

Since its inception, the Computation Structures Group has worked on issues at the boundary between computer architecture and programming methodology. The emphasis has been on providing support for exploiting parallelism in computations while maintaining, or improving, the ease of developing robust software. Recognizing that the functional programming style provides a medium for expressing parallelism without violating principles of modular software construction, the group has focused on computer architecture concepts and principles that offer the ability to execute efficiently programs expressed in the functional style. The Monsoon project [2] was an important milestone in demonstrating that appropriately designed processors can achieve effective parallel execution of software written without use of explicit operations for indicating possibilities for parallel execution. Another emphasis of the group's work has been on the benefits of implementing a global address space for all information, data and procedures, shared by users of a computer system. These benefits were demonstrated in the Project MAC Multics system and have been realized in the commercial world in the successful AS/400 series of computer systems offered by IBM.

The Fresh Breeze project aims to realize these benefits through a new single-chip multiprocessor architecture, making an attack on the problem considered to be the major issue in contemporary computer architecture: how to organize multiple processors on a chip so that their power can be effectively coordinated and applied.

Approach

The proposed multiprocessor chip [1] will incorporate three ideas that are significant departures from conventional thinking about multiprocessor architecture:

Simultaneous multithreading. Simultaneous multithreading has been shown to have performance advantages relative to contemporary superscalar designs. This advantage can be exploited through use of a programming model that exposes parallelism in the form of multiple threads of computation.

Global shared address space. The value of a shared address space is widely appreciated. Through the use of 64-bit pointers, the conventional distinction between ''memory'' and the file system can be abolished. This will provide a superior execution environment in support of program modularity and software reuse.

No memory update; cycle-free heap. Data items are created, used, and released, but never modified once created. The allocation, release, and garbage collection of fixed-size chunks of memory will be implemented by efficient hardware mechanisms. A major benefit of this choice is that the multiprocessor cache coherence problem vanishes: any object retrieved from the memory system is immutable. In addition, it is easy to prevent the formation of pointer cycles, simplifying the design of memory management support.

The design and evaluation of a novel architecture and programming model for a general purpose multiprocessor chip is proposed. The chip will include eight to sixteen processors, each of which is of simultaneous multithread organization and capable of superscalar performance. The memory model will support a 64-bit address space of 1024-bit ''chunks'' of memory used to hold programs and data shared by all users. Active chunks will be held in on-chip fully associative cache units, and ''paged'' to off-chip memory when replaced by newly active chunks. Chunks of data are created, initialized, accessed, shared, and released, but are never updated. The result is a system in which there is no cache consistency issue, implementing security of memory access is straightforward, and memory management is readily implemented in hardware. Application programming will be supported in the Java programming language, restricted so that that the Secure Arguments principle for modular software components is satisfied, and so that implicit parallelism can be the basis for achieving high levels of parallel processing performance. The work to be performed includes building a cycle-accurate simulation of the multiprocessor chip, developing a translator from Java bytecode class files to the multithread instruction set, and evaluating the programmability and performance of the simulated system for representative benchmark codes and applications.

Status and Plans

A cycle-accurate simulator for the Multithread processor has been programmed in Java and will be extended to model a complete Fresh Breeze chip. In coming months it is expected that the simulator will be tested and used to evaluate the Fresh Breeze programming model and architecture.  Work has begun on building a compiler that translates and optimizes Java bytecode class files to machine code for the multithread processor. Once these tools are in place, the merit of the Fresh Breeze ideas will be tested for a variety of applications. Success in this work will provide justification for development of an FPGA prototype of the multiprocessor using the RAMP prototyping board.

References

[1] Jack B. Dennis. Fresh Breeze: A multiprocessor chip architecture guided by modular programming principles. ACM Sigarch News, March 2003.

[2] G. M. Papadopoulos and D. E. Culler. Monsoon: an explicit token-store architecture. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pp 82-91, IEEE Computer Society, 1990.